*-* Dual-Metal Gate Technology for Deep-Submicron CMOS Transistors

نویسندگان

  • Qiang Lu
  • Yee Chia Yeo
  • Pushkar Ranade
  • Hideki Takeuchi
  • Tsu-Jae King
  • Chenming Hu
  • H. F. Luan
  • Dim-Lee Kwong
چکیده

Dual-metal gate CMOS devices with rapid-thermal chemicalvapor deposited (RTCVD) Si3N4 gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and MO for the Nand PMOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for Si02. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Gate Engineering for Deep-Submicron CMOS Transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET’s. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET’s is investigated. The suppression of...

متن کامل

Intel’s 45nm CMOS Technology

For the 45nm technology node, high-k+metal gate transistors have been introduced for the first time in a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled a 0.7x reduction in Tox while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion...

متن کامل

Analog Design in Deep Submicron Cmos Processes for Lhc

Present state-of-the-art CMOS technologies integrate MOS transistors with a minimum gate length of 0.18 Pm0.25 Pm and operate with a maximum power supply of 2.5 V. The thin gate oxide used in these technologies has a high tolerance to total dose effects. Therefore, circuits designed in these technologies using dedicated layout techniques (enclosed layout transistors and guard-rings) show a tota...

متن کامل

Analysis of Nonuniform ESD Current Distribution in Deep Submicron NMOS Transistors

This paper presents a detailed study of the nonuniform bipolar conduction phenomenon under electrostatic discharge (ESD) events in single-finger NMOS transistors and analyzes its implications for the design of ESD protection for deep-submicron CMOS technologies. It is shown that the uniformity of the bipolar current distribution under ESD conditions is severely degraded depending on device fing...

متن کامل

Design and Analysis of a Novel Low-Power SRAM Bit-Cell Structure at Deep-Sub-Micron CMOS Technology for Mobile Multimedia Applications

The growing demand for high density VLSI circuits and the exponential dependency of the leakage current on the oxide thickness is becoming a major challenge in deep-submicron CMOS technology. In this work, a novel Static Random Access Memory (SRAM) Cell is proposed targeting to reduce the overall power requirements, i.e., dynamic and standby power in the existing dual-bit-line architecture. The...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2004